1. Field of the Invention
The present invention relates to a semiconductor device and a method of producing the same, in particular to a highly integrated circuit, a vertical type transistor exhibiting high transition frequency and current gain and an integrated circuit containing the transistor therein and a method of producing the same.
2. Description of the Prior Art
A method of producing the conventional NPN transistor will be described with reference to FIG. 1. As shown in FIG. 1(A), a P-type silicon substrate is used as a semiconductor substrate 41, antimony being selectively deposited on a surface of the substrate 41 to form an N.sup.+ -type buried layer 43, and boron being deposited on a surface of the substrate 41 surrounding the buried layer 43 to form a lower diffusion layer of a double isolation diffusion area 44 (see FIG. 1(D)).
Then, as shown in FIG. 1(B), an N-type epitaxial layer 42 is grown on the substrate 41. Boron is deposited on a surface of the epitaxial layer 42 at positions corresponding to the lower diffusion layer 44' to form an upper diffusion layer 44" of the double isolation diffusion area 44.
Subsequently, as shown in FIG. 1(C), the upper diffusion layer 44" and the lower diffusion layer 44' of the double isolation diffusion area 44 and the buried layer 43 are diffused in the epitaxial layer 42 by heating the substrate 41, to connect the upper diffusion layer 44" with the lower diffusion layer 44', whereby forming the double isolation diffusion area 44. This diffusion process is carried out for 3 to 4 hours at about 1,100.degree. C. If the epitaxial layer 42 is 13 .mu.m thick, the upper diffusion layer 44" is outdiffused downwardly about 10 .mu.m in depth while the lower diffusion layer 44' is outdiffused upwardly about 5 .mu.m in depth.
In addition, as shown in FIG. 1(D), a P-type base area 46 and an N-type emitter area 47 are diffused on a surface of an island 45 formed with the epitaxial layer 42 surrounded by the double isolation diffusion area 44, and a collector contact area 48 is diffused on a surface of the island 45 simultaneously with the emitter area 47.
Thus, an NPN transistor is formed in the island 45.
In the case where the isolation area 44 is formed by the downward diffusion and the upward diffusion in the above described manner, the diffusion time is shorter than that in the conventional method in which the isolation area is formed by diffusing only from the upper side since the upper diffusion layer 44" contains impurities at a higher ratio, but since the upper diffusion layer 44" is to be diffused thicker than the lower diffusion layer 44', it is necessary to diffuse the former thicker than the latter and thus, a lateral diffusion is increased. In short, an area to be occupied by the upper diffusion layer 44" in the epitaxial layer 42 is large, whereby the integrated extent is prevented from being improved.
On the other hand, the vertical type PNP transistor has the problems described below:
The conventional vertical type PNP transistor, as shown in FIG. 2, comprises an N-type epitaxial layer 52 grown on a surface of a P-type silicon semiconductor substrate 51, an N.sup.+ -type buried layer 53 formed on the substrate 51, a double isolation diffusion area 54 passing through the epitaxial layer 52 so as to completely surround the buried layer 53, a P.sup.+ -type collector area 55 overlaid on the buried layer 53 of the substrate 51, a P.sup.+ -type collector-leading area 56 extending to the collector area 55 from a surface of the epitaxial layer 52, a base area 57 completely surrounded by the collector area 55 and the collector-leading area 56 and formed of the epitaxial layer 52, a P.sup.+ -type emitter area 58 formed on a surface of the base area 57, an oxidized film 59 covering a surface of the epitaxial layer 52, and a collector electrode 61, a base electrode 62 and an emitter electrode 63 being brought into ohmic contact with the collector-leading area 56, the base contact area 60 and the emitter area 58, respectively, through an electrode hole of the oxidized film 59. Such a vertical type PNP transistor has been disclosed in, for example, Japanese Patent Laid-Open No. 59-172738 (1984). In this construction, since the base area 57 is formed of the epitaxial layer 52, the concentration of impurities is low to an extent of 10.sup.16 cm.sup.-3 or less, and since a breadth size (a size in the direction of thickness) is large, a defect has been that the transition frequency f.sub.T is low. In addition, since the specific resistance and the thickness of the epitaxial layer 52 are apt to fluctuate and this fluctuation results from the fluctuation of the base area 57 in concentration of impurities and breadth size, a defect has been that the current gain h.sub.FE of the PNP transistor fluctuates due to such a fluctuation.
A vertical type PNP transistor, in which such a defect was eliminated, is shown in FIG. 3. This vertical type PNP transistor is provided with a P-type silicon semiconductor substrate 71, an N-type epitaxial layer 72 formed on the substrate 71, an N.sup.+ -type buried layer 73 formed on the substrate 71, a P.sup.+ -type double isolation diffusion area 74 passing through the epitaxial layer 72 so as to completely surround the buried layer 73, a P.sup.+ -type collector area 75 formed on the buried layer 73, a P.sup.+ -type collector-leading area 76 extending from a surface of the epitaxial layer 72 to the collector area 75, a base area 77 completely surrounded by the collector area 75 and the collector-leading area 76 and formed of the epitaxial layer 72, a P.sup.+ -type emitter area 78 formed on a surface of the base area 77, an N.sup.+ -type base contact area 80 formed on a surface of the base area 77, an oxidized film 79 covering a surface of the epitaxial layer 72, a collector electrode 81, a base electrode 82 and an emitter electrode 83 being brought into ohmic contact with the collector-leading area 76, the base contact area 80 and the emitter area 78, respectively, through an electrode hole of this oxidized film 79, and an N-type ion implantation area 84 having the concentration of impurities higher than that of the base area 77 formed on a surface of the base area 77.
Referring to FIG. 4, which is a profile showing the concentration of impurities in this transistor, the concentration of impurities of the N-type ion implantation area 84 formed on a surface of the epitaxial layer 72 is about 10 times higher than that of the epitaxial layer 72. The base area 77 is composed of the epitaxial layer 72 and the ion implantation area 84. Accordingly, since the concentration of impurities in the base area 77 is tend to be reduced from the emitter area 78 to the collector area 75, a drift electric field is generated within the base area 77, whereby accelerating a hole. As a result, the transition frequency f.sub.T of a vertical type PNP transistor shown in FIG. 3, which is 100 MHz, is remarkably higher than that of a transistor shown in FIG. 2 which is 50 MHz.
In addition, since the h.sub.FE of a vertical type PNP transistor is almost determined by the depth of the ion implantation area 84 even though the thickness and specific resistance of the epitaxial layer 72 fluctuate, the fluctuation of h.sub.FE is remarkably reduced by the ion implantation. Concretely speaking, it becomes about 1/2 time reduced than that in the conventional one. But, since the breadth size of the base area 77 is large, the improvement of the transition frequency f.sub.T is limited. In addition, the fluctuation of h.sub.FE due to the fluctuation of the epitaxial layer 72 in thickness cannot be evitable. Furthermore, since the concentration of impurities in the collector area 75 is small to an extent of 10.sup.17 cm.sup.-3, a defect occurs that the collector emitter saturated voltage V.sub.CE (sat) is large.